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CPU Details
General
Manufacturer MOS
Part Number 6502
Architecture width 8
Introduction date September 1975
Initial price $25
Architecture
Number of Cores 1
Data bus width 8
Address bus width 16
Instruction set 6502
Speed
Max speed 3MHz
Memory
Max RAM 64kiB
Technology
Process technology NMOS
Process size 16 µm
Transistors 3510
Die size 21 mm²
Modules
Power
Core voltage 5V
I/O voltage 5V
Package
Package DIP
Pins 40
Socket DIP
Other
Links
Wikipedia MOS_Technology_6502
v · d · e

The MOS Technology 6502 is an 8-bit microprocessor that was designed by Chuck Peddle and Bill Mensch for MOS Technology in 1975. When it was introduced, it was the least expensive full-featured microprocessor on the market by a considerable margin, costing less than one-sixth the price of competing designs from larger companies such as Motorola and Intel. It was nevertheless fully comparable with them and, along with the Zilog Z80, sparked a series of computer projects that would eventually result in the home computer revolution of the 1980s. The 6502 design was originally second-sourced by Rockwell and Synertek and later licensed to a number of companies. Soon after the 6502's introduction, MOS Technology was bought outright by Commodore International, who continued to sell the chip to other manufacturers.

DetailsEdit


ImagesEdit


Bugs and quirksEdit

  • The earliest revisions of the 6502, such as those shipped with some KIM-1 computers, had a severe bug in the ROR (rotate right memory or accumulator) instruction. The operation of ROR in these chips is effectively an ASL instruction that does not update the carry status bit. MOS left the instruction out of chip documentation entirely because of the defect, promising that ROR would appear on 6502 chips starting in 1976.[1] The vast majority of 6502 chips in existence today do not exhibit this bug.
  • The original 6502 and its NMOS derivatives are noted for having a variety of undocumented instructions, which vary from one chip manufacturer to the next. The 6502's instruction decoding is implemented in a hardwired logic array (similar to a programmable logic array) which is only defined for 151 of the 256 available opcodes. The remaining 105 trigger strange and hard-to-predict actions (e.g., immediately crashing the processor, performing several valid instructions at once, or simply doing nothing at all). Eastern House Software developed the "Trap65", a device that plugged between the processor and its socket to convert (trap) unimplemented opcodes into BRK (software interrupt) instructions. Some programmers utilized this feature to extend the 6502's instruction set by providing functionality for the unimplemented opcodes with specially written software intercepted at the BRK instruction's 0xFFFE vector. All of the undefined opcodes have been replaced by NOP instructions in the WDC 65C02 CMOS version, although with varying byte sizes and execution times. In the 65C816, all 256 opcodes perform defined operations.
  • The 6502's memory indirect jump instruction, JMP (<address>), is partially broken. If <address> is hex xxFF (i.e., any word ending in FF), the processor will not jump to the address stored in xxFF and xxFF+1 as expected, but rather the one defined by xxFF and xx00. This defect continued through the entire NMOS line, but was corrected in the CMOS derivatives.
  • The NMOS 6502's indexed addressing across page boundaries will do an extra read of invalid address. This can cause issues by accessing hardware that acts on a read (e.g., clearing timer or IRQ flags, sending an I/O handshake, etc.). This defect continued through the entire NMOS line, but was fixed in the CMOS derivatives, in which the processor does an extra read of the last instruction byte.
  • The 6502's read/modify/write instructions perform one read and two write cycles. This characteristic may cause issues by twice accessing hardware that acts on a write. This anomaly continued through the entire NMOS line, but was fixed in the CMOS derivatives, in which the processor will do two reads and one write cycle. Good programming practice will generally avoid executing read/modify/write instructions on hardware registers.
  • The N (result negative), V (sign bit overflow) and Z (result zero) status flags are not valid when performing arithmetic operations while the processor is in BCD mode, as these flags reflect the binary, not BCD, result. This limitation was removed in the CMOS derivatives. Therefore, this feature may be used to cleanly distinguish CMOS from NMOS CPU versions without using any illegal opcodes.[2]
  • If the processor happens to be in BCD mode when a hardware interrupt occurs it will not revert to binary mode. This quirk could result in hard-to-solve bugs in the interrupt service routine if it fails to clear BCD mode before performing any arithmetic operations. For example, the Commodore 64's kernel did not correctly handle this processor characteristic, requiring that IRQs be disabled or revectored during BCD math operations. This issue was addressed in the CMOS derivatives as well.
  • The 6502 instruction set includes BRK (opcode $00), which is technically a software interrupt (similar in spirit to the SWI mnemonic of the 6800 and ARM processors). BRK is most often used to interrupt program execution and start a machine code monitor for testing and debugging during software development. It could also be used to route program execution using a simple jump table (analogous to the manner in which the 8088 and derivatives handle software interrupts by number). Unfortunately, if a hardware interrupt occurs at the same time the processor is fetching a BRK instruction, the NMOS version of the processor will fail to execute BRK and instead proceed as if only a hardware interrupt had occurred. This fault was corrected in the CMOS implementation of the processor.
  • When executing JSR (jump to subroutine) and RTS (return from subroutine) instructions, the return address pushed to the stack by JSR is that of the last byte of the JSR operand (that is, the most significant byte of the subroutine address), rather than the address of the following instruction. This is because the actual copy (from program counter to stack and then vice-versa) takes place before the automatic increment of the program counter that occurs at the end of every instruction.[3] This characteristic would go unnoticed unless you pulled the return address to pick up parameters in the code stream (a common 6502 programming idiom). It remains a characteristic of 6502 derivatives to this day.


Support ChipsEdit

  • MOS 6520 - Peripheral Interface Adapter (PIA)
  • MOS 6522 - Versatile Interface Adapter (VIA)
  • MOS 6523 - Tri-Port Interface (TPI)
  • MOS 6525 - Tri-Port Interface (TPI)
  • MOS 6526 - Complex Interface Adapter (CIA)
  • MOS 6529 - Single Port Interface Adapter (SPIA)
  • MOS 6530 - ROM-RAM-I/O Timer (RRIOT)
  • MOS 6532 - RIOT RAM-I/O Timer (RIOT)
  • MOS 6545 - CRT Controller (CRTC)
  • MOS 6551 - Asynchronous Communications Interface Adapter (ACIA)
  • MOS 6560 - Video Interface Chip (VIC) (NTSC)
  • MOS 6561 - Video Interface Chip (VIC) (PAL)
  • MOS 6564 - 80-column video
  • MOS 6567 - Video Interface Chip II (VIC-II) (NTSC)
  • MOS 6569 - Video Interface Chip II (VIC-II) (PAL)
  • MOS 6570 - Keyboard processor
  • MOS 6571 - Keyboard processor
  • MOS 6581 - Sound Interface Device (SID)


Chip VariantsEdit

ReferencesEdit

  1. "Measuring the ROR Bug in the Early MOS 6502". http://www.pagetable.com/?p=406. Retrieved 8 May 2011. 
  2. Draco (19 June 1997). "65c02, 6502, 65816 ??? CPU sells but who`s buying...". Archived from the original on 2 January 2008. http://replay.waybackmachine.org/20080102014138/http://www.s-direktnet.de/homepages/k_nadj/cputest.html. 
  3. Andrews, Mark (1984). "6". Atari Roots - A Guide To Atari Assembly Language. Template:Hide in printTemplate:Only in print. http://www.atariarchives.org/roots/chapter_6.php. 

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